DRIE Etching for Glass and Silicon Microstructures

Deep Reactive Ion Etching (DRIE) is used to create deep, narrow and near-vertical microstructures in glass, fused silica, silicon and related substrates. It is suitable for through-glass vias, through-silicon vias, MEMS structures, microfluidic channels, photonic components and high-density nozzle arrays.

Available processes include ICP-RIE for glass and SiO₂, Bosch DRIE for silicon, and cryogenic DRIE for silicon or polymer substrates. Minimum feature size can reach 1 μm, with etch depth up to 500 μm for silicon Bosch processing and up to 200 μm for glass ICP-RIE. Aspect ratio can reach up to 50:1 for silicon and up to 30:1 for glass.

We can process custom DRIE substrates from GDS-II or DXF mask designs, with support for wafer-level and panel-level processing. Available documentation can include etch depth maps, SEM images, profilometry data and process records.

What Is Deep Reactive Ion Etching (DRIE)?

Deep Reactive Ion Etching (DRIE) is an advanced plasma-based dry etching process that uses alternating cycles of etching and passivation — known as the Bosch process — or cryogenic cooling to achieve highly anisotropic material removal with near-vertical sidewalls and extremely high depth-to-diameter ratios. In the Bosch process, a sulfur hexafluoride (SF₆) plasma etch cycle removes material isotropically, followed immediately by a C₄F₈ passivation cycle that deposits a protective polymer layer on all surfaces. Because the ion bombardment from the plasma preferentially removes the passivation layer from horizontal surfaces (the etch front) while leaving sidewall protection intact, the net result is directional etching that advances vertically with minimal lateral undercut. This cycle repeats hundreds of times per micron of depth, producing the characteristic scalloped sidewall texture of Bosch-process DRIE. For glass and fused silica, fluorine-based ICP-RIE without the Bosch cycle is typically used, achieving smoother sidewalls at the cost of slightly lower aspect ratios. DRIE is the enabling technology for MEMS accelerometers, pressure sensors, microfluidic devices, through-silicon vias (TSV), through-glass vias (TGV), and any application requiring deep, narrow, vertical features in semiconductor or optical substrates.

Process Capabilities

Etch Systems: ICP-RIE (glass / SiO₂) · Bosch DRIE (silicon) · Cryogenic DRIE (Si / polymer)
Minimum Feature Size: 1 µm (lithography-limited)
Maximum Etch Depth: 500 µm (silicon Bosch) · 200 µm (glass ICP-RIE)
Depth-to-Diameter Ratio: Up to 50:1 (Bosch Si) · Up to 30:1 (glass ICP-RIE)
Sidewall Angle: 88° – 90° (Bosch) · 85° – 88° (glass ICP-RIE)
Etch Rate: 2 – 10 µm/min (glass ICP-RIE) · 5 – 20 µm/min (Si Bosch)
Depth Uniformity: ±2% across 150 mm wafer

Compatible Materials

1	Fused Silica	Corning 7980 / Tosoh ES-2000
2	Quartz Glass	SCHOTT Lithosil Q / Heraeus Suprasil 1
3	Borosilicate Glass	PYREX 7740 / BOROFLOAT 33
4	Silicon	Float Zone / Czochralski — mono / poly
5	Sapphire	C-plane / A-plane
6	Glass-Ceramic	ZERODUR / PYROCERAM 9606
7	SiO₂ Thin Film	Thermal oxide / PECVD oxide
8	Si₃N₄	LPCVD / PECVD nitride
9	CaF₂	UV-grade
10	Optical Glass	BK7 / N-BK7
11	Technical Ceramics	Al₂O₃ / AlN

Process Strategy Selection

Bosch Process (Si): Alternating SF₆ etch + C₄F₈ passivation cycles — highest AR (50:1), slight scalloping (50–200 nm), best for deep silicon MEMS and TSV
Glass ICP-RIE (SF₆/Ar or C₄F₈/SF₆): Continuous fluorine plasma — smooth sidewalls, AR up to 30:1, best for fused silica TGV and microfluidic features
Cryogenic DRIE (Si, –100°C): Low-temperature condensation replaces C₄F₈ passivation — smoother sidewalls than Bosch, better for sub-micron features
Hard Mask Selection: Photoresist (depth ≤ 20 µm) · SiO₂ (≤ 100 µm) · Ni/Cr metal (≤ 500 µm)
ARDE Compensation: Aspect-ratio-dependent etching correction applied for uniform depth across mixed feature sizes

Typical Applications

Through-Glass Vias (TGV): Vertical interconnect vias in glass interposers for 3D IC and advanced packaging
MEMS Structures: Proof masses, comb drives, cantilevers, and membrane release in silicon and glass
Microfluidic Devices: Vertical-wall channels and chambers in fused silica for high-pressure lab-on-chip
Photonic Components: Ridge waveguides, photonic crystal structures, and grating couplers
Nozzle Plates: High-density inkjet and dispensing nozzle arrays with precise bore geometry
Inertial Sensors: Accelerometer and gyroscope proof-mass structures in silicon-on-glass

Custom Specifications

We accept custom DRIE orders based on GDS-II or DXF mask designs, supporting both wafer-level and panel-level processing. Custom parameters include etch depth, sidewall angle, scallop amplitude, hard mask selection, and aspect-ratio-dependent etching (ARDE) compensation for uniform depth across mixed feature sizes. Integrated workflows combining photolithography, DRIE, mask stripping, and post-etch metrology — including SEM cross-section inspection, profilometry, and wafer bow measurement — are available as a complete turnkey service. For TGV and TSV applications, downstream via filling (electroless Cu / polymer plug) and CMP planarization are also available. All processed substrates are delivered with full etch depth maps, SEM images, and process documentation.